The present invention relates to a semiconductor memory device.
A conventional semiconductor memory device will be described with reference to FIG. 5. This semiconductor memory is an EPROM having memory cells disposed in a matrix form. Each of the memory cells is a MOSFET having a floating gate and a control gate. Each of memory cells MC11, MC12, . . . , MCmn stores a binary data. Each of reference cells DC1, DC2, . . . , DCm is a MOSFET having a floating gate, too.
The gates of the memory cells and a reference cell at each row are connected to each row or word line WL1, WL2, . . . , WLm, the drains of memory cells at each column are connected to each column or bit line BL1, BL2, . . . , BLn, and the drain of reference cells are connected to a reference column or reference bit line DBL. Each memory cell is selected by a column decoder 12 and a row decoder 11. Column gate transistors BT1, BT2, . . . , BTn select one of the column lines. The transistor DBT connected to the reference bit line DBL performs a function equivalent to the function of the column gate transistor.
A first load circuit 13 includes MOSFETs QM1 to QM12. The first load circuit 13 amplifies the data from a selected memory cell and outputs it to a data detection circuit 15. A second load circuit 34 includes MOSFETs QD1 to QD12. The second load circuit 34 amplifies the data from a selected reference cell and outputs it to the data detection circuit 15. The data detection circuit 15 compares the data from the selected memory cell with the data from the selected reference cell, and detects the data stored in the selected memory cell and then outputs it to an output buffer. The following is a description of the read operation of the data detection circuit 15 for reading the data stored in a memory cell of the EPROM constructed as above.
Data is programmed in the memory cell by injecting electrons into the floating gate. If the floating gate of a memory cell is injected electrons, it remains off even if a logic "1" level signal is applied to the control gate. If the floating gate of the memory cell is not injected with electrons, the memory cell is turned on when a logic "1" level signal is applied to the control gate of the memory cell. Electrons are not injected in the floating gate of a reference cell so that it is electrically equivalent to the memory cell which has not been injected electrons.
In the first load circuit 13, the data stored in a selected memory cell is amplified and output as a potential V.sub.IN. Similarly, in the second load circuit 34, the data of a selected reference cell is amplified and output as a reference potential V.sub.REF. These potentials V.sub.IN and V.sub.REF are supplied to the data detection circuit 15 which compares them with each other to thereby detect and output the data stored in the memory cell.
As shown in FIG. 6, the data detection circuit 15 is constructed, for example, as a difference sense amplifier having p-channel MOSFETs T21 and T22 and n-channel MOSFETs T23 and T24. The reference potential V.sub.REF is applied to the gate of the MOSFET T22, and the potential V.sub.IN is applied to the gate of MOSFET T21. As shown in FIG. 7, if a selected memory cell is not injected electrons (indicated at time duration t1), the memory cell is turned on and the potential V.sub.IN lowers. On the other hand, if a selected memory cell is injected electrons (indicated at time duration t2), the memory cell is turned off and the potential V.sub.IN is charged by the load transistor QM5 and the potential V.sub.IN becomes high.
If the first and second load circuits 13 and 34 are constructed of the same circuit, the reference potential V.sub.REF is the same potential as that when a selected memory cell is not injected electrons (indicated at time duration t1), as shown by a one-dot chain line. Such a reference potential V.sub.REF cannot be used as a reference potential for detecting the data stored in the memory cell. In order to get a potential difference between the reference potential V.sub.REF and the potential V.sub.IN for the memory cell which is not injected electrons, the reference potential V.sub.REF is set substantially at the middle value between the potential V.sub.IN for the memory cell which is injected electrons and the potential V.sub.IN for the memory cell which is not injected electrons, as shown by a broken line.
If different voltages are applied to the gates of the reference cell and the memory cell, we get the potential difference between the reference potential V.sub.REF and the potential V.sub.IN with the first and second load circuits 13 and 34 constructed of the same circuit. In this case, since the gates of the memory cell and the reference cell are connected to different signal lines the influence of power source noise on the memory cell is different from the influence of power source noise on the reference cell. Consequently, erroneous operation occurs, when more power source noise is generated. However, the gates of the memory cell and the reference cell are connected to the same row lines WL1 to WLm in order to undergo the same influence of power source noise and to suppress erroneous operation caused by the power source noise. Therefore, the potential difference is obtained by using the different size transistors as the load transistors QM5 and QD5 of the first and second load circuits 13 and 34, respectively. Namely, the channel width of the transistor QD5 is wider than that of the transistor QM5 to raise the reference potential V.sub.REF to the broken line level.
With the above arrangement, since there is a difference in the current supply capability between transistors QM5 and QD5, the column line (BL1, BL2, . . . , BLn) and the reference column line (DBL) are influenced differently by power source noise. There still remains the problem that erroneous operation due to power source noise cannot be eliminated entirely.